AArch64: simplify PCS mapping.

AArch64: simplify PCS mapping.

Now that LLVM can count the registers needed to implement AAPCS rules, we don't
need to duplicate that logic here. This means we can drop the explicit padding
and also use more natural types in many cases (e.g. "struct { float arr[3]; }"
used to end up as "[2 x double]" to avoid holes on the stack.

The one wrinkle is that AAPCS va_arg was also using the register counting
machinery. But the local replacement isn't too bad.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@222904 91177308-0d34-0410-b5e6-96231b3b80d8