]> granicus.if.org Git - llvm/commit
[InstCombine] Teach SimplifyDemandedInstructionBits that even if we reach an instruct...
authorCraig Topper <craig.topper@gmail.com>
Wed, 12 Apr 2017 18:17:46 +0000 (18:17 +0000)
committerCraig Topper <craig.topper@gmail.com>
Wed, 12 Apr 2017 18:17:46 +0000 (18:17 +0000)
commit51f7e1a9dc71abd06ac4050937f82f078fe1cabb
treee14d56b0360ab448d248531a1fff9a50ce13af7c
parent6b814345d13a9dc5a67ce590f8a3ee4345ac2fc9
[InstCombine] Teach SimplifyDemandedInstructionBits that even if we reach an instruction that has multiple uses, if we know all the bits for the demanded bits for this context we can go ahead and create a constant.

Currently if we reach an instruction with multiples uses we know we can't do any optimizations to that instruction itself since we only have the demanded bits for one of the users. But if we know all of the bits are zero/one for that one user we can still go ahead and create a constant to give to that user.

This might then reduce the instruction to having a single use and allow additional optimizations on the other path.

This picks up an additional case that r300075 didn't catch.

Differential Revision: https://reviews.llvm.org/D31552

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300084 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
test/Transforms/InstCombine/and2.ll