]> granicus.if.org Git - llvm/commit
[X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit...
authorCraig Topper <craig.topper@intel.com>
Wed, 14 Aug 2019 14:52:39 +0000 (14:52 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 14 Aug 2019 14:52:39 +0000 (14:52 +0000)
commit50d3b49c52f990127ec90172ef411cc2b10ad1dc
tree4c5d5ced3413ad97d748aad6215ac9492534911c
parent02fc1512cd0076f79ebee25fd2b5e5d4a0ae56c3
[X86][CostModel] Adjust the costs of ZERO_EXTEND/SIGN_EXTEND with less than 128-bit inputs

Now that we legalize by widening, the element types here won't change. Previously these were modeled as the elements being widened and then the instruction might become an AND or SHL/ASHR pair. But now they'll become something like a ZERO_EXTEND_VECTOR_INREG/SIGN_EXTEND_VECTOR_INREG.

For AVX2, when the destination type is legal its clear the cost should be 1 since we have extend instructions that can produce 256 bit vectors from less than 128 bit vectors. I'm a little less sure about AVX1 costs, but I think the ones I changed were definitely too high, but they might still be too high.

Differential Revision: https://reviews.llvm.org/D66169

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368858 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86TargetTransformInfo.cpp
test/Analysis/CostModel/X86/cast.ll
test/Analysis/CostModel/X86/extend.ll
test/Analysis/CostModel/X86/min-legal-vector-width.ll
test/Transforms/SLPVectorizer/X86/cast.ll
test/Transforms/SLPVectorizer/X86/sext.ll
test/Transforms/SLPVectorizer/X86/zext.ll