]> granicus.if.org Git - esp-idf/commit
uart: fix uart_tx_wait_idle to wait for fifo empty
authorIvan Grokhotkov <ivan@espressif.com>
Mon, 15 Oct 2018 12:08:16 +0000 (20:08 +0800)
committerIvan Grokhotkov <ivan@espressif.com>
Mon, 15 Oct 2018 12:08:16 +0000 (20:08 +0800)
commit508fb79a26a9b62e9b3007b98169a2bc2005594d
treeb27bbf4ac6b5678e2b673b24aa100bff7bd4f835
parent88625a25010ccbdf4ec4eb7a97a8835ccc622a31
uart: fix uart_tx_wait_idle to wait for fifo empty

In some cases, when data was just written into UART FIFO, transmitter
state could be still zero while the FIFO did contain some data.
This resulted in uart_tx_wait_idle occasionally returning before all
the data was sent out.
Fix by checking both UART transmitter state and TX FIFO count.
components/esp32/include/rom/uart.h
components/esp32/sleep_modes.c