[AArch64][SVE] Allow explicit size specifier for predicate operand

[AArch64][SVE] Allow explicit size specifier for predicate operand

... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue
supporting the exsting behaviour of not requiring an explicit size
specifier. The preferred disasembly is *with* the specifier.

This is implemented by redefining intruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.

Differential Revision: https://reviews.llvm.org/D65145

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367019 91177308-0d34-0410-b5e6-96231b3b80d8