]> granicus.if.org Git - llvm/commit
[X86] Enable custom splitting of v8i64/v16i32 sext/zext for avx/avx2 when input type...
authorCraig Topper <craig.topper@intel.com>
Sat, 23 Feb 2019 00:35:02 +0000 (00:35 +0000)
committerCraig Topper <craig.topper@intel.com>
Sat, 23 Feb 2019 00:35:02 +0000 (00:35 +0000)
commit4c3f72beaa9a7486ed0746a9545cebe56b0654dd
treedcea7f40fe4e9522f61d7a838792ec2f5d7e75e2
parent483b6a88f82c7d74cd2f9f8b8a7672f93935b652
[X86] Enable custom splitting of v8i64/v16i32 sext/zext for avx/avx2 when input type will be promoted by the type legalize to 128-bits.

If the the input type will be promoted to 128 bits its better to put a sign_extend_inreg/and in the 128 bit register before the split occurs. Otherwise we end up doing it on each half in the wider register.

Some of the overflow arithmetic tests are regressions, but I think we can make some improvement using getSetccResultType in DAG combine and/or type legalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354709 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/vec_saddo.ll
test/CodeGen/X86/vec_smulo.ll
test/CodeGen/X86/vec_ssubo.ll
test/CodeGen/X86/vec_uaddo.ll
test/CodeGen/X86/vec_umulo.ll
test/CodeGen/X86/vec_usubo.ll
test/CodeGen/X86/vector-sext-widen.ll
test/CodeGen/X86/vector-sext.ll
test/CodeGen/X86/vector-zext-widen.ll
test/CodeGen/X86/vector-zext.ll