]> granicus.if.org Git - llvm/commit
[SVE][Inline-Asm] Add constraints for SVE predicate registers
authorKerry McLaughlin <kerry.mclaughlin@arm.com>
Mon, 16 Sep 2019 09:45:27 +0000 (09:45 +0000)
committerKerry McLaughlin <kerry.mclaughlin@arm.com>
Mon, 16 Sep 2019 09:45:27 +0000 (09:45 +0000)
commit48d00babac84a3b489c038cd01ec86a279e002ab
treea8634c948475dd5611c9a8b58216c967c26c9f8c
parent911a837b3dcb2c625fec4e6523e27ea65478833c
[SVE][Inline-Asm] Add constraints for SVE predicate registers

Summary:
Adds the following inline asm constraints for SVE:
  - Upl: One of the low eight SVE predicate registers, P0 to P7 inclusive
  - Upa: SVE predicate register with full range, P0 to P15

Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened, rengolin

Reviewed By: rovka

Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371967 91177308-0d34-0410-b5e6-96231b3b80d8
docs/LangRef.rst
lib/IR/InlineAsm.cpp
lib/Target/AArch64/AArch64AsmPrinter.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/AArch64/AArch64InstrInfo.cpp
test/CodeGen/AArch64/aarch64-sve-asm.ll