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(parent: 0614ded) | patch
Add Intel BMI1, BMI2, INVPCID, LZCNT instructions.
authorPeter Johnson <peter@tortall.net>
Sun, 3 Jul 2011 08:48:44 +0000 (01:48 -0700)
committerPeter Johnson <peter@tortall.net>
Sun, 3 Jul 2011 08:48:44 +0000 (01:48 -0700)
commit47f693fd89b5d961e7097674c21263060299b10c
tree7c70ba9389bddbae2605c7ee84a1384e4e90bdc4tree | snapshot
parent0614dede9bb5b285804882cf71479f4e9757ec2fcommit | diff
Add Intel BMI1, BMI2, INVPCID, LZCNT instructions.

Reference: http://www.intel.com/software/avx rev11 spec

Also add appropriate CPU bits and directive handling for these.

Currently we have no good way of handling an "or" of instruction bits
(in this case needed for LZCNT, where it's either AMD or LZCNT).  For
now, make it LZCNT only.

Contributed by: Mark Charney <mark.charney@intel.com>

Part of [#227].
12 files changed:
modules/arch/x86/gen_x86_insn.py diff | blob | history
modules/arch/x86/tests/Makefile.inc diff | blob | history
modules/arch/x86/tests/bmi1.asm [new file with mode: 0644] blob
modules/arch/x86/tests/bmi1.hex [new file with mode: 0644] blob
modules/arch/x86/tests/bmi2.asm [new file with mode: 0644] blob
modules/arch/x86/tests/bmi2.hex [new file with mode: 0644] blob
modules/arch/x86/tests/invpcid.asm [new file with mode: 0644] blob
modules/arch/x86/tests/invpcid.hex [new file with mode: 0644] blob
modules/arch/x86/tests/lzcnt.asm [new file with mode: 0644] blob
modules/arch/x86/tests/lzcnt.hex [new file with mode: 0644] blob
modules/arch/x86/x86arch.h diff | blob | history
modules/arch/x86/x86cpu.gperf diff | blob | history
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