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[Mips][Codegen] Fix fast-isel mixing of FGR64 and AFGR64 registers
authorSimon Atanasyan <simon@atanasyan.com>
Fri, 9 Aug 2019 12:02:32 +0000 (12:02 +0000)
committerSimon Atanasyan <simon@atanasyan.com>
Fri, 9 Aug 2019 12:02:32 +0000 (12:02 +0000)
commit476a92cf77923fc4b088ec225bae19a3d2af97ed
treeb3b178d2320233a7916bc1176c30a1d60006dc10tree | snapshot
parent728185772afa89c3bb47423fac9109fd970529b8commit | diff
[Mips][Codegen] Fix fast-isel mixing of FGR64 and AFGR64 registers

Fast-isel was picking AFGR64 register class for processing call
arguments when +fp64 options was used. We simply check is option +fp64
is used and pick appropriate register.

Patch by Mirko Brkusanin.

Differential Revision: https://reviews.llvm.org/D65886

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368433 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MipsFastISel.cpp diff | blob | history
test/CodeGen/Mips/copy-fp64.ll [new file with mode: 0644] blob
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