]> granicus.if.org Git - llvm/commit
Improve machine schedulers for in-order processors
authorJaved Absar <javed.absar@arm.com>
Mon, 27 Mar 2017 20:46:37 +0000 (20:46 +0000)
committerJaved Absar <javed.absar@arm.com>
Mon, 27 Mar 2017 20:46:37 +0000 (20:46 +0000)
commit47652291c2db94da417f9d8b3d10185b200a4a8f
treeab01f8550ae73cb57eb0716ab1e34345f6213d2e
parent3903b47a909d6ef870aa29146c119a42b67277c1
Improve machine schedulers for in-order processors

This patch enables schedulers to specify instructions that
cannot be issued with any other instructions.
It also fixes BeginGroup/EndGroup.

Reviewed by: Andrew Trick
Differential Revision: https://reviews.llvm.org/D30744

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298885 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/TargetSchedule.h
include/llvm/Target/TargetSchedule.td
lib/CodeGen/MachineScheduler.cpp
lib/CodeGen/TargetSchedule.cpp
lib/Target/ARM/ARMScheduleR52.td
test/CodeGen/ARM/single-issue-r52.mir [new file with mode: 0644]
utils/TableGen/SubtargetEmitter.cpp