]> granicus.if.org Git - llvm/commit
[X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly...
authorCraig Topper <craig.topper@intel.com>
Mon, 22 Jul 2019 19:58:49 +0000 (19:58 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 22 Jul 2019 19:58:49 +0000 (19:58 +0000)
commit46cba73063fd8b5a11b155615b2bd801b90b916f
tree774365214f30e2c1de391152504502e5493fb9c0
parent8481559a37d871d0a3601410b4d6ce2aa816461e
[X86] When using AND+PACKUS in lowerV16I8Shuffle, generate the build vector directly in v16i8 with the correct 0x00 or 0xFF elements rather than using another VT and bitcasting it.

The build_vector will become a constant pool load. By using the
desired type initially, it ensures we don't generate a bitcast
of the constant pool load which will need to be folded with
the load.

While experimenting with another patch, I noticed that when the
load type and the constant pool type don't match, then
SimplifyDemandedBits can't handle it. While we should probably
fix that, this was a simple way to fix the issue I saw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366732 91177308-0d34-0410-b5e6-96231b3b80d8
16 files changed:
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avg.ll
test/CodeGen/X86/masked_store_trunc.ll
test/CodeGen/X86/mmx-arith.ll
test/CodeGen/X86/oddshuffles.ll
test/CodeGen/X86/oddsubvector.ll
test/CodeGen/X86/psubus.ll
test/CodeGen/X86/sse2-intrinsics-canonical.ll
test/CodeGen/X86/vector-reduce-and-bool.ll
test/CodeGen/X86/vector-reduce-or-bool.ll
test/CodeGen/X86/vector-reduce-xor-bool.ll
test/CodeGen/X86/vector-shuffle-128-v16.ll
test/CodeGen/X86/vector-trunc-math-widen.ll
test/CodeGen/X86/vector-trunc-math.ll
test/CodeGen/X86/vector-trunc-widen.ll
test/CodeGen/X86/vector-trunc.ll