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IRgen: Fix case where we might generate an access component with width == 0, if
authorDaniel Dunbar <daniel@zuster.org>
Thu, 22 Apr 2010 14:56:10 +0000 (14:56 +0000)
committerDaniel Dunbar <daniel@zuster.org>
Thu, 22 Apr 2010 14:56:10 +0000 (14:56 +0000)
commit4651efb5ba5710c91b58c8b86872b264dd71f464
tree297d6c8fc50a0a239c7e1e01f145be4ab09a5c76tree | snapshot
parent66dd9394994654b5af2c62ed24f311432bacede5commit | diff
IRgen: Fix case where we might generate an access component with width == 0, if
we have to narrow the access side immediately (can happen with packed,
-fno-bitfield-type-align).

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@102067 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/CGRecordLayoutBuilder.cpp diff | blob | history
test/CodeGen/bitfield-2.c diff | blob | history
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