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[PowerPC] Fix sjlj pseduo instructions to use G8RC_NOX0 register class
authorKit Barton <kbarton@ca.ibm.com>
Wed, 1 Feb 2017 14:33:57 +0000 (14:33 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Wed, 1 Feb 2017 14:33:57 +0000 (14:33 +0000)
commit447c100995d02e6acd0cac9f3967c5b82a1d161c
tree3bdb5786b3bb22670d28b1d426675fd4419d2d5btree | snapshot
parent30afc90a6020478b7cef900957a58bccf83e5c7ccommit | diff
[PowerPC] Fix sjlj pseduo instructions to use G8RC_NOX0 register class

The the following instructions:
  - LD/LWZ (expanded from sjLj pseudo-instructions)
  - LXVL/LXVLL vector loads
  - STXVL/STXVLL vector stores
all require G8RC_NO0X class registers for RA.

Differential Revision: https://reviews.llvm.org/D29289

Committed for Lei Huang

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293769 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/PPCInstrInfo.td diff | blob | history
test/CodeGen/PowerPC/sjlj_no0x.ll [new file with mode: 0644] blob
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