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(parent: 505187a) | patch
[FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved.
authorJuergen Ributzka <juergen@apple.com>
Tue, 14 Oct 2014 20:36:02 +0000 (20:36 +0000)
committerJuergen Ributzka <juergen@apple.com>
Tue, 14 Oct 2014 20:36:02 +0000 (20:36 +0000)
commit40017084f71d7e93ed57ed395f375b249d690952
tree75fb3a32d26e08fe22ec00b0e210704f74a0f67btree | snapshot
parent505187a9bd6beb779d3ae76b44efa69a72f68173commit | diff
[FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved.

Sign-/zero-extend folding depended on the load and the integer extend to be
both selected by FastISel. This cannot always be garantueed and SelectionDAG
might interfer. This commit adds additonal checks to load and integer extend
lowering to catch this.

Related to rdar://problem/18495928.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219716 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64FastISel.cpp diff | blob | history
test/CodeGen/AArch64/fast-isel-int-ext2.ll [new file with mode: 0644] blob
test/CodeGen/AArch64/fast-isel-int-ext3.ll [new file with mode: 0644] blob
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