]> granicus.if.org Git - esp-idf/commit
soc: add invalid cache access interrupt bits to dport_reg
authorIvan Grokhotkov <ivan@espressif.com>
Wed, 12 Apr 2017 09:48:59 +0000 (17:48 +0800)
committerIvan Grokhotkov <ivan@espressif.com>
Thu, 13 Apr 2017 07:27:38 +0000 (15:27 +0800)
commit3c6c1e36ec2586020c12e311870b994c61a9fc00
treec6d484670c8ce1d67d6f0d6e2f707c1494da7951
parent82b7ca92ad4e652f31b429a36c54131cf2d80898
soc: add invalid cache access interrupt bits to dport_reg
components/soc/esp32/include/soc/dport_reg.h