]> granicus.if.org Git - llvm/commit
[DAGCombine][ARM] Enable extending masked loads
authorSam Parker <sam.parker@arm.com>
Thu, 17 Oct 2019 07:55:55 +0000 (07:55 +0000)
committerSam Parker <sam.parker@arm.com>
Thu, 17 Oct 2019 07:55:55 +0000 (07:55 +0000)
commit3a4bfa616e88c6c7b1f8df9907a65731dae08766
tree15cd2dd10a04d424e8e33af59f4b67e8e71f0fbc
parent2078d8cdd74943911886d703887f4a4169558d7c
[DAGCombine][ARM] Enable extending masked loads

Add generic DAG combine for extending masked loads.

Allow us to generate sext/zext masked loads which can access v4i8,
v8i8 and v4i16 memory to produce v4i32, v8i16 and v4i32 respectively.

Differential Revision: https://reviews.llvm.org/D68337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375085 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMInstrMVE.td
lib/Target/ARM/ARMTargetTransformInfo.cpp
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
test/CodeGen/Thumb2/mve-masked-ldst.ll
test/CodeGen/Thumb2/mve-masked-load.ll
test/CodeGen/Thumb2/mve-masked-store.ll
test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll