]> granicus.if.org Git - llvm/commit
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid...
authorCraig Topper <craig.topper@intel.com>
Sun, 10 Mar 2019 17:20:45 +0000 (17:20 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 10 Mar 2019 17:20:45 +0000 (17:20 +0000)
commit385eaa67a35b51d8c8bd173d376ac8ff7f5325aa
tree78695c5bc508ccae1593788bad05519280dd24f3
parent3d8d3321c08b34638ff5b7440f09138a0b4de971
[X86] Make lowering of intrinsics with rounding mode stricter so that only valid rounding modes are lowered. Update tests accordingly

Many of our tests were not using valid rounding mode immediates. Clang verifies this in the frontend when it creates the intrinsics from builtins, but the backend would still lower invalid immediates.

With this change we will now leave them as intrinsics if the immediate is invalid. This will cause an isel selection failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355789 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avx512-fma-intrinsics-upgrade.ll
test/CodeGen/X86/avx512-fma-intrinsics.ll
test/CodeGen/X86/avx512-intrinsics-upgrade.ll
test/CodeGen/X86/avx512-intrinsics-x86_64.ll
test/CodeGen/X86/avx512-intrinsics.ll
test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll
test/CodeGen/X86/avx512dq-intrinsics.ll
test/CodeGen/X86/fma-fneg-combine.ll