[InstCombine] fold sign-bit compares of srem

[InstCombine] fold sign-bit compares of srem

(srem X, pow2C) sgt/slt 0 can be reduced using bit hacks by masking
off the sign bit and the module (low) bits:
https://rise4fun.com/Alive/jSO
A '2' divisor allows slightly more folding:
https://rise4fun.com/Alive/tDBM

Any chance to remove an 'srem' use is probably worthwhile, but this is limited
to the one-use improvement case because doing more may expose other missing
folds. That means it does nothing for PR21929 yet:
https://bugs.llvm.org/show_bug.cgi?id=21929

Differential Revision: https://reviews.llvm.org/D67334

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371610 91177308-0d34-0410-b5e6-96231b3b80d8