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[RISCV] Add support for floating point registers in inlineasm
authorSimon Cook <simon.cook@embecosm.com>
Wed, 31 Jul 2019 09:12:00 +0000 (09:12 +0000)
committerSimon Cook <simon.cook@embecosm.com>
Wed, 31 Jul 2019 09:12:00 +0000 (09:12 +0000)
commit379d9dbd5081ee106b40ef58cf1df0fb82ef55d1
tree8c595a8f27e26260de8da5c52a86d19ab9229681tree | snapshot
parent8396f4d402cfec5cdd671f000e087f42fb5f4fefcommit | diff
[RISCV] Add support for floating point registers in inlineasm

This adds support for parsing/emitting in IR the floating-point RISC-V
registers in inline assembly clobber lists.

Differential Revision: https://reviews.llvm.org/D64737

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@367399 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Basic/Targets/RISCV.cpp diff | blob | history
test/Sema/riscv-asm.c [new file with mode: 0644] blob
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