]> granicus.if.org Git - llvm/commit
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
authorShiva Chen <shiva0217@gmail.com>
Wed, 28 Aug 2019 23:40:37 +0000 (23:40 +0000)
committerShiva Chen <shiva0217@gmail.com>
Wed, 28 Aug 2019 23:40:37 +0000 (23:40 +0000)
commit3767f18861be3f8ad2b2f3e8caad022946debc6e
tree6adc1a40982461100b374293fd548308cd8fc9f2
parent7d610ade1d38fd0d8e5513446c26d4bc2838ca8f
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall

The patch fixed the issue that RV64 didn't clear the upper bits
when return complex floating value with lp64 ABI.

float _Complex
complex_add(float _Complex a, float _Complex b)
{
   return a + b;
}

RealResult = zero_extend(RealA + RealB)
ImageResult = ImageA + ImageB
Return (RealResult | (ImageResult << 32))

The patch introduces shouldExtendTypeInLibCall target hook to suppress
the AssertZext generation when lowering floating LibCall.

Thanks to Eli's comments from the Bugzilla
https://bugs.llvm.org/show_bug.cgi?id=42820

Differential Revision: https://reviews.llvm.org/D65497

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370275 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/TargetLowering.h
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
lib/CodeGen/SelectionDAG/TargetLowering.cpp
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/RISCV/RISCVISelLowering.cpp
lib/Target/RISCV/RISCVISelLowering.h
test/CodeGen/RISCV/calling-conv-lp64.ll
test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
test/CodeGen/RISCV/rv64i-complex-float.ll [new file with mode: 0644]
test/CodeGen/RISCV/rv64i-single-softfloat.ll [new file with mode: 0644]