]> granicus.if.org Git - llvm/commit
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Thu, 13 Jul 2017 18:17:10 +0000 (18:17 +0000)
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Thu, 13 Jul 2017 18:17:10 +0000 (18:17 +0000)
commit35b282e0ac388a13e5d3c5fcb27b39693b79ae33
treead8656b4ab76b9a2f9d819a22711d4555665a144
parent4632cb1499e0cd57b5b986371e4bd4dff1b0f6cf
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16

As outlined in the PR, we didn't ensure that displacements for DQ-Form
instructions are multiples of 16. Since the instruction encoding encodes
a quad-word displacement, a sub-16 byte displacement is meaningless and
ends up being encoded incorrectly.

Fixes https://bugs.llvm.org/show_bug.cgi?id=33671.

Differential Revision: https://reviews.llvm.org/D35007

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307934 91177308-0d34-0410-b5e6-96231b3b80d8
12 files changed:
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.h
lib/Target/PowerPC/PPCInstrInfo.td
lib/Target/PowerPC/PPCInstrVSX.td
lib/Target/PowerPC/PPCRegisterInfo.cpp
test/CodeGen/PowerPC/PR33671.ll [new file with mode: 0644]
test/CodeGen/PowerPC/build-vector-tests.ll
test/CodeGen/PowerPC/ppc64-i128-abi.ll
test/CodeGen/PowerPC/swaps-le-6.ll
test/CodeGen/PowerPC/vsx-p9.ll