]> granicus.if.org Git - llvm/commit
[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).
authorHuihui Zhang <huihuiz@quicinc.com>
Sat, 15 Jun 2019 00:33:41 +0000 (00:33 +0000)
committerHuihui Zhang <huihuiz@quicinc.com>
Sat, 15 Jun 2019 00:33:41 +0000 (00:33 +0000)
commit34a27682ed02e6273e91b49bacf6bfc75e8da157
tree7fd0bb35c87db5364a624f734ec539b67c7c123a
parentdaecbabf55cf11efe6edcd40df96ae7e9359ecf5
[InstCombine] Add tests to show missing fold opportunity for "icmp and shift" (nfc).

Summary:
For icmp pred (and (sh X, Y), C), 0

  When C is signbit, expect to fold (X << Y) & signbit ==/!= 0 into (X << Y) >=/< 0,
  rather than (X & (signbit >> Y)) != 0.

  When C+1 is power of 2, expect to fold (X << Y) & ~C ==/!= 0 into (X << Y) </>= C+1,
  rather than (X & (~C >> Y)) == 0.

For icmp pred (and X, (sh signbit, Y)), 0

  Expect to fold (X & (signbit l>> Y)) ==/!= 0 into (X << Y) >=/< 0
  Expect to fold (X & (signbit << Y)) ==/!= 0 into (X l>> Y) >=/< 0

  Reviewers: lebedev.ri, efriedma, spatel, craig.topper

  Reviewed By: lebedev.ri

  Subscribers: llvm-commits

  Tags: #llvm

  Differential Revision: https://reviews.llvm.org/D63025

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363479 91177308-0d34-0410-b5e6-96231b3b80d8
test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll [new file with mode: 0644]
test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll [new file with mode: 0644]
test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll [new file with mode: 0644]
test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll [new file with mode: 0644]
test/Transforms/InstCombine/signbit-lshr-and-icmpeq-zero.ll [new file with mode: 0644]
test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll [new file with mode: 0644]