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[GlobalISel][X86] Support bitwise operations : G_AND, G_OR, G_XOR
authorIgor Breger <igor.breger@intel.com>
Wed, 28 Jun 2017 11:39:04 +0000 (11:39 +0000)
committerIgor Breger <igor.breger@intel.com>
Wed, 28 Jun 2017 11:39:04 +0000 (11:39 +0000)
commit31bb0eb5180b79f461dfb2b4fe99a2d6074befba
tree4e836d3a8015a38dd850071a05ccb48b71b2d87dtree | snapshot
parentfd3c664b13736ea5d26501c440d3317d4a48b80fcommit | diff
[GlobalISel][X86] Support bitwise operations : G_AND, G_OR, G_XOR

Summary: Support G_AND, G_OR, G_XOR for i8/i16/i32/i64. Selection done via TableGen'erated code.

Reviewers: zvi, guyblank, aymanmus, m_zuckerman

Reviewed By: aymanmus

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34605

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306533 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86LegalizerInfo.cpp diff | blob | history
test/CodeGen/X86/GlobalISel/and-scalar.ll [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/or-scalar.ll [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir diff | blob | history
test/CodeGen/X86/GlobalISel/select-and-scalar.mir [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/select-or-scalar.mir [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/select-xor-scalar.mir [new file with mode: 0644] blob
test/CodeGen/X86/GlobalISel/xor-scalar.ll [new file with mode: 0644] blob
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