]> granicus.if.org Git - llvm/commit
[PowerPC] P9 Scheduling Model: dispatching rule fixes
authorJinsong Ji <jji@us.ibm.com>
Tue, 4 Jun 2019 15:22:23 +0000 (15:22 +0000)
committerJinsong Ji <jji@us.ibm.com>
Tue, 4 Jun 2019 15:22:23 +0000 (15:22 +0000)
commit319cfe2ad01124973dec578c0c5e187bc779813a
tree128afbaff95c2049438c11ccc97169523940be2b
parent47d861e4bff0755e5595db9b7cf22f1e2bcfbd83
[PowerPC] P9 Scheduling Model: dispatching rule fixes

This is to address some of the problems in existing P9 resource modeling,
especially about the dispatching rules.

Instead of using a hypothetical DISPATCHER , we try to use the number of
actual dispatch slots, and define SchedWriteRes to model dispatch rules,
then update instruction classes according to dispatch rules.

All the dispatch rules and instruction classes update are made according
to POWER9 User Manual.

Differential Revision: https://reviews.llvm.org/D61873

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362509 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/P9InstrResources.td
lib/Target/PowerPC/PPCScheduleP9.td
test/CodeGen/PowerPC/build-vector-tests.ll
test/CodeGen/PowerPC/csr-save-restore-order.ll
test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll