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[X86][SSE] Merge SSE2 PINSRW lowering with SSE41 PINSRB/PINSRW lowering. NFCI.
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 1 Feb 2017 13:32:19 +0000 (13:32 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 1 Feb 2017 13:32:19 +0000 (13:32 +0000)
commit30afc90a6020478b7cef900957a58bccf83e5c7c
tree1294d1b0c5b64acc5a5341d47af6f444e4bf3186tree | snapshot
parent47d1df4cfdc4ae809e6d57792734422231c6c896commit | diff
[X86][SSE] Merge SSE2 PINSRW lowering with SSE41 PINSRB/PINSRW lowering. NFCI.

These are identical apart from the extra SSE41 guard for PINSRB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293766 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp diff | blob | history
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