]> granicus.if.org Git - llvm/commit
[DAGCombiner] exclude x*2.0 from normal negation profitability rules
authorSanjay Patel <spatel@rotateright.com>
Fri, 9 Aug 2019 21:37:32 +0000 (21:37 +0000)
committerSanjay Patel <spatel@rotateright.com>
Fri, 9 Aug 2019 21:37:32 +0000 (21:37 +0000)
commit2cc159477ad165523fd8142ed97c3257fc3cbeda
tree96d4cb28282d1e88c0a40095d658c64fde818b3c
parente9e1af1f24d41e5b3a32ae9c32254e31b52762f2
[DAGCombiner] exclude x*2.0 from normal negation profitability rules

This is the codegen part of fixing:
https://bugs.llvm.org/show_bug.cgi?id=32939

Even with the optimal/canonical IR that is ideally created by D65954,
we would reverse that transform in DAGCombiner and end up with the same
asm on AArch64 or x86.

I see 2 options for trying to correct this:

  1. Limit isNegatibleForFree() by special-casing the fmul pattern (this patch).
  2. Avoid creating (fmul X, 2.0) in the 1st place by adding a special-case
     transform to SelectionDAG::getNode() and/or SelectionDAGBuilder::visitFMul()
     that matches the transform done by DAGCombiner.

This seems like the less intrusive patch, but if there's some other reason to
prefer 1 option over the other, we can change to the other option.

Differential Revision: https://reviews.llvm.org/D66016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368490 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/AArch64/fadd-combines.ll
test/CodeGen/X86/fadd-combines.ll