]> granicus.if.org Git - llvm/commit
[mips][msa] Fix generation of bm(n)zi and bins[lr]i instructions
authorPetar Jovanovic <petar.jovanovic@imgtec.com>
Fri, 7 Apr 2017 13:31:36 +0000 (13:31 +0000)
committerPetar Jovanovic <petar.jovanovic@imgtec.com>
Fri, 7 Apr 2017 13:31:36 +0000 (13:31 +0000)
commit2ad61e77494ca29c86d4c4365cf50c1c11842463
treecebb1a4c56ab12f4ed80fa8d65a90254febc639c
parent7bf2a5770da8fa53e08e0b27c46bf3ad798bbbf9
[mips][msa] Fix generation of bm(n)zi and bins[lr]i instructions

We have two cases here, the first one being the following instruction
selection from the builtin function:
bm(n)zi builtin -> vselect node -> bins[lr]i machine instruction

In case of bm(n)zi having an immediate which has either its high or low bits
set, a bins[lr] instruction can be selected through the selectVSplatMask[LR]
function. The function counts the number of bits set, and that value is
being passed to the bins[lr]i instruction as its immediate, which in turn
copies immediate modulo the size of the element in bits plus 1 as per specs,
where we get the off-by-one-error.

The other case is:
bins[lr]i -> vselect node -> bsel.v

In this case, a bsel.v instruction gets selected with a mask having one bit
less set than required.

Patch by Stefan Maksimovic.

Differential Revision: https://reviews.llvm.org/D30579

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299768 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
lib/Target/Mips/MipsSEISelLowering.cpp
test/CodeGen/Mips/msa/bitwise.ll
test/CodeGen/Mips/msa/bmzi_bmnzi.ll [new file with mode: 0644]
test/CodeGen/Mips/msa/i5-b.ll
test/CodeGen/Mips/msa/immediates.ll