]> granicus.if.org Git - llvm/commit
[X86] Use packusdw+vpmovuswb to implement v16i32->V16i8 that clamps signed inputs...
authorCraig Topper <craig.topper@intel.com>
Thu, 10 Oct 2019 19:40:44 +0000 (19:40 +0000)
committerCraig Topper <craig.topper@intel.com>
Thu, 10 Oct 2019 19:40:44 +0000 (19:40 +0000)
commit2acd87bbf2b487324fa12df9525ba7335725709f
tree1ec3631fb5a6cd4bbc4e4669c47b2523b5fe9d4b
parent2e5e103c861402fbaae4f3a5fda348944baecb12
[X86] Use packusdw+vpmovuswb to implement v16i32->V16i8 that clamps signed inputs to be between 0 and 255 when zmm registers are disabled on SKX.

If we've disable zmm registers, the v16i32 will need to be split. This split will propagate through min/max the truncate. This creates two sequences that need to be concatenated back to v16i8. We can instead use packusdw to do part of the clamping, truncating, and concatenating all at once. Then we can use a vpmovuswb to finish off the clamp.

Differential Revision: https://reviews.llvm.org/D68763

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374431 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/min-legal-vector-width.ll