]> granicus.if.org Git - llvm/commit
[AVX-512] Don't use unmasked VMOVDQU8/16 for 8-bit or 16-bit element stores even...
authorCraig Topper <craig.topper@intel.com>
Tue, 1 Aug 2017 15:31:24 +0000 (15:31 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 1 Aug 2017 15:31:24 +0000 (15:31 +0000)
commit2a519cbde98d695959baf8f5f6017092f10aa30a
tree9ca01ce28167eb6d8afe8f5e6cccb48e4dc61142
parente1059016008d9c162dc8ac70f54fb099028427c1
[AVX-512] Don't use unmasked VMOVDQU8/16 for 8-bit or 16-bit element stores even when BWI instructions are supported. Always use VMOVDQA32/VMOVDQU32.

We were already using the 32 bit element opcode if BWI isn't enabled, but there's no reason to change opcode if we have BWI. We will still use the 8/16 opcodes for masked stores though.

This allows us to use the aligned opcode when we can which makes our test output more consistent between different modes. It also reduces the number of isel patterns we need.

This is a slight inconsistency with loads which default to 64 bit element opcodes. I'll probably rectify that in a future patch.

Differential Revision: https://reviews.llvm.org/D35978

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309693 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrAVX512.td
test/CodeGen/X86/avg.ll
test/CodeGen/X86/avx512-insert-extract.ll
test/CodeGen/X86/avx512-insert-extract_i1.ll
test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
test/CodeGen/X86/avx512bw-mov.ll
test/CodeGen/X86/avx512bwvl-mov.ll
test/CodeGen/X86/subvector-broadcast.ll
test/CodeGen/X86/x86-interleaved-access.ll