[AVR] Fix displacement overflow for LDDW/STDW

[AVR] Fix displacement overflow for LDDW/STDW

In some cases, the code generator attempts to generate instructions such as:

lddw r24, Y+63

which expands to:

ldd r24, Y+63
ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary

This commit limits the first offset to 62, and thus the second to 63.
It also updates some asserts in AVRExpandPseudoInsts.cpp, including for
INW and OUTW, which appear to be unused.

Patch by Thomas Backman.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314890 91177308-0d34-0410-b5e6-96231b3b80d8