]> granicus.if.org Git - llvm/commit
[X86] Add more ISD nodes to handle masked versions of VCVT(T)PD2DQZ128/VCVT(T)PD2UDQZ...
authorCraig Topper <craig.topper@intel.com>
Sun, 13 Jan 2019 02:59:59 +0000 (02:59 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 13 Jan 2019 02:59:59 +0000 (02:59 +0000)
commit27d15ecc2b8c8a8c9642374058ee13ba5389fd64
treec5de587dc9b3927097382c452429a24245f70cdb
parent47100f5f523424a284c2ccf3f9442179aa27d6d4
[X86] Add more ISD nodes to handle masked versions of VCVT(T)PD2DQZ128/VCVT(T)PD2UDQZ128 which only produce 2 result elements and zeroes the upper elements.

We can't represent this properly with vselect like we normally do. We also have to update the instruction definition to use a VK2WM mask instead of VK4WM to represent this.

Fixes another case from PR34877

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351018 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86IntrinsicsInfo.h