]> granicus.if.org Git - llvm/commit
[mips] Place certain 64 bit FPU instructions in their own decoder namespace
authorSimon Dardis <simon.dardis@imgtec.com>
Thu, 5 Oct 2017 10:27:37 +0000 (10:27 +0000)
committerSimon Dardis <simon.dardis@imgtec.com>
Thu, 5 Oct 2017 10:27:37 +0000 (10:27 +0000)
commit27b9512501c946880d371dd244be9c702affe22a
tree07e1deeb7883052cb5058a527b901be3211d2338
parentb71dbeaf08fad916a2ebd7594fab61aa6b2a32a7
[mips] Place certain 64 bit FPU instructions in their own decoder namespace

Previously, instructions that were defined to use the FGR64 register class
were associated with the Mips64 table which was incorrect.

Reviewers: nitesh.jain, atanasyan

Differential Revision: https://reviews.llvm.org/D38454

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314976 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
lib/Target/Mips/MicroMips32r6InstrInfo.td
lib/Target/Mips/MipsCondMov.td
lib/Target/Mips/MipsInstrFPU.td
test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt