Fix type of last vector operand of Neon quad-register multiple-lane intrinsics.

Fix type of last vector operand of Neon quad-register multiple-lane intrinsics.
The sensible thing would be to have these intrinsics take all quad-register
vector operands, but that's not what ARM did.  They made the last vector
operand always be a double-register type.  Since the lane number
must be a constant, the user can know which half of a quad-register contains
that lane, extract the high or low half of the vector, and adjust the lane
number accordingly.  The only advantage I can see for this is that it works
better when you want to multiply a quad-register value by a lane from a
double-register value, but I wouldn't have expected that to be the common
case.  Oh well -- at this point we just need to follow the spec.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@121397 91177308-0d34-0410-b5e6-96231b3b80d8