]> granicus.if.org Git - llvm/commit
[mips][mt][6/7] Add support for mftr, mttr instructions.
authorSimon Dardis <simon.dardis@imgtec.com>
Wed, 12 Jul 2017 19:47:45 +0000 (19:47 +0000)
committerSimon Dardis <simon.dardis@imgtec.com>
Wed, 12 Jul 2017 19:47:45 +0000 (19:47 +0000)
commit1ece62aab5f5b40da116710cf85ae2444b357bb2
tree48e3e4d44bfdd45f3b93e66ad193ab54df5886a5
parentde79ef835a32134be62803556875a3158ae425ac
[mips][mt][6/7] Add support for mftr, mttr instructions.

Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.

For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35253

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307836 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
lib/Target/Mips/MipsMTInstrFormats.td
lib/Target/Mips/MipsMTInstrInfo.td
lib/Target/Mips/MipsSchedule.td
lib/Target/Mips/MipsTargetStreamer.h
test/MC/Disassembler/Mips/mt/valid-r2-el.txt
test/MC/Disassembler/Mips/mt/valid-r2.txt
test/MC/Mips/mt/invalid-wrong-error.s [new file with mode: 0644]
test/MC/Mips/mt/invalid.s
test/MC/Mips/mt/mftr-mttr-aliases-invalid-wrong-error.s [new file with mode: 0644]
test/MC/Mips/mt/mftr-mttr-aliases-invalid.s [new file with mode: 0644]
test/MC/Mips/mt/mftr-mttr-aliases.s [new file with mode: 0644]
test/MC/Mips/mt/mftr-mttr-reserved-valid.s [new file with mode: 0644]
test/MC/Mips/mt/valid.s