]> granicus.if.org Git - llvm/commit
GlobalISel: Change representation of shuffle masks
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 13 Aug 2019 15:34:38 +0000 (15:34 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 13 Aug 2019 15:34:38 +0000 (15:34 +0000)
commit1dcdc3296340a1b5fc0626b250917a2f52a228f4
tree85622113d99e427269f5194cebc3a7ba5259d735
parentc285223daf7f38a17188ae0f788a67731a70470c
GlobalISel: Change representation of shuffle masks

Currently shufflemasks get emitted as any other constant, and you end
up with a bunch of virtual registers of G_CONSTANT with a
G_BUILD_VECTOR. The AArch64 selector then asserts on anything that
doesn't fit this pattern. This isn't an ideal representation, and
should avoid legalization and have fewer opportunities for a
representational error.

Rather than invent a new shuffle mask operand type, similar to what
ShuffleVectorSDNode does, just track the original IR Constant mask
operand. I don't completely like the idea of adding another link to
the IR, but MIR is already quite dependent on IR constants already,
and this will allow sharing the shuffle mask utility functions with
the IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@368704 91177308-0d34-0410-b5e6-96231b3b80d8
25 files changed:
include/llvm/CodeGen/MachineInstrBuilder.h
include/llvm/CodeGen/MachineOperand.h
include/llvm/Target/GenericOpcodes.td
lib/CodeGen/GlobalISel/IRTranslator.cpp
lib/CodeGen/MIRParser/MILexer.cpp
lib/CodeGen/MIRParser/MILexer.h
lib/CodeGen/MIRParser/MIParser.cpp
lib/CodeGen/MIRPrinter.cpp
lib/CodeGen/MachineOperand.cpp
lib/CodeGen/MachineVerifier.cpp
lib/Target/AArch64/AArch64InstructionSelector.cpp
lib/Target/ARM/ARMExpandPseudoInsts.cpp
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir
test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir
test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir
test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
test/CodeGen/MIR/AArch64/parse-shufflemask-invalid0.mir [new file with mode: 0644]
test/CodeGen/MIR/AArch64/parse-shufflemask-invalid1.mir [new file with mode: 0644]
test/CodeGen/MIR/AArch64/parse-shufflemask-invalid2.mir [new file with mode: 0644]
test/CodeGen/MIR/AArch64/parse-shufflemask-invalid3.mir [new file with mode: 0644]
test/CodeGen/MIR/AArch64/parse-shufflemask.mir [new file with mode: 0644]
test/MachineVerifier/test_g_shuffle_vector.mir [new file with mode: 0644]