]> granicus.if.org Git - llvm/commit
AMD family 17h (znver1) scheduler model update.
authorAshutosh Nema <ashu1212@gmail.com>
Thu, 31 Aug 2017 12:38:35 +0000 (12:38 +0000)
committerAshutosh Nema <ashu1212@gmail.com>
Thu, 31 Aug 2017 12:38:35 +0000 (12:38 +0000)
commit1914cbfcb681ee9f264c1b5fb28e6cd4daa8249b
treeb4ee1ba1819cf281cdeb1f263eaa84a7c3017afe
parent43878499027fd679b32fd66877235806666f0aaa
AMD family 17h (znver1) scheduler model update.

Summary:
This patch enables the following:
1) Regex based Instruction itineraries for integer instructions.
2) The instructions are grouped as per the nature of the instructions
   (move, arithmetic, logic, Misc, Control Transfer).
3) FP instructions and their itineraries are added which includes values
   for SSE4A, BMI, BMI2 and SHA instructions.

Patch by Ganesh Gopalasubramanian

Reviewers: RKSimon, craig.topper

Subscribers: vprasad, shivaram, ddibyend, andreadb, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D36617

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312237 91177308-0d34-0410-b5e6-96231b3b80d8
20 files changed:
lib/Target/X86/X86ScheduleZnver1.td
test/CodeGen/X86/aes-schedule.ll
test/CodeGen/X86/avx-schedule.ll
test/CodeGen/X86/avx2-schedule.ll
test/CodeGen/X86/bmi-schedule.ll
test/CodeGen/X86/bmi2-schedule.ll
test/CodeGen/X86/f16c-schedule.ll
test/CodeGen/X86/lea32-schedule.ll
test/CodeGen/X86/lea64-schedule.ll
test/CodeGen/X86/lzcnt-schedule.ll
test/CodeGen/X86/movbe-schedule.ll
test/CodeGen/X86/popcnt-schedule.ll
test/CodeGen/X86/sha-schedule.ll
test/CodeGen/X86/sse-schedule.ll
test/CodeGen/X86/sse2-schedule.ll
test/CodeGen/X86/sse3-schedule.ll
test/CodeGen/X86/sse41-schedule.ll
test/CodeGen/X86/sse42-schedule.ll
test/CodeGen/X86/sse4a-schedule.ll
test/CodeGen/X86/ssse3-schedule.ll