]> granicus.if.org Git - llvm/commit
projects / llvm / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: de0ded9) | patch
[PowerPC] more opportunity for converting reg+reg to reg+imm
authorChen Zheng <czhengsz@cn.ibm.com>
Wed, 30 Jan 2019 01:57:01 +0000 (01:57 +0000)
committerChen Zheng <czhengsz@cn.ibm.com>
Wed, 30 Jan 2019 01:57:01 +0000 (01:57 +0000)
commit16cbc63cb07d0f4b3385fb47d5f352de04f85c3f
tree1db03da02a869e32cf3a8c912b8598cc08f5e03dtree | snapshot
parentde0ded95baeb3222e88035610ef4362adc52cb81commit | diff
[PowerPC] more opportunity for converting reg+reg to reg+imm
Differential Revision: https://reviews.llvm.org/D57314

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352583 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/PPCInstrInfo.cpp diff | blob | history
test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir [new file with mode: 0644] blob
Unnamed repository; edit this file 'description' to name the repository.