[RISCV] Prepare for the use of variable-sized register classes

[RISCV] Prepare for the use of variable-sized register classes

While parameterising by XLen, also take the opportunity to clean up the
formatting of the RISCV .td files.

This commit unifies the in-tree code with my patchset at
<https://github.com/lowrisc/riscv-llvm>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316159 91177308-0d34-0410-b5e6-96231b3b80d8