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[AMDGPU] Change register type for v32 vectors
authorStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Tue, 16 Jul 2019 20:06:00 +0000 (20:06 +0000)
committerStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Tue, 16 Jul 2019 20:06:00 +0000 (20:06 +0000)
commit10f786ca0ffdabfacd9ea60168488ee16d95c7e4
treef6bcf3ca80eb3ca7daa348c3821ea8e6965ed706tree | snapshot
parentf8b274f2cb444e179b6f9f6115f48f162a0154cacommit | diff
[AMDGPU] Change register type for v32 vectors

When it is AReg_1024 this results in unnecessary copying into
AGPRs of a 32 element vectors even though they are not intended
for an mfma instruction.

Differential Revision: https://reviews.llvm.org/D64815

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366252 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
test/CodeGen/AMDGPU/v1024.ll [new file with mode: 0644] blob
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