]> granicus.if.org Git - llvm/commit
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
authorDaniel Sanders <daniel_l_sanders@apple.com>
Thu, 19 Jan 2017 11:15:55 +0000 (11:15 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Thu, 19 Jan 2017 11:15:55 +0000 (11:15 +0000)
commit1086a51e178ee71549ac4251d3a0ba1ccce6e1b3
tree1e56dda116e86bff63c85051b5d7747b93cec141
parente3ad0db135e354ab3b6b734834c81e5b9e4cb07d
Re-commit: [globalisel] Tablegen-erate current Register Bank Information

Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.

Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals

Reviewers: t.p.northover, ab, rovka, qcolombet

Reviewed By: qcolombet

Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka

Differential Revision: https://reviews.llvm.org/D27338

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292478 91177308-0d34-0410-b5e6-96231b3b80d8
17 files changed:
include/llvm/CodeGen/GlobalISel/RegisterBank.h
include/llvm/Target/GlobalISel/RegisterBank.td [new file with mode: 0644]
include/llvm/Target/Target.td
lib/CodeGen/GlobalISel/RegisterBank.cpp
lib/Target/AArch64/AArch64.td
lib/Target/AArch64/AArch64GenRegisterBankInfo.def
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
lib/Target/AArch64/AArch64RegisterBankInfo.h
lib/Target/AArch64/AArch64RegisterBanks.td [new file with mode: 0644]
lib/Target/AArch64/AArch64TargetMachine.cpp
lib/Target/AArch64/CMakeLists.txt
lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/Target/GlobalISel/RegisterBank.td [new file with mode: 0644]
utils/TableGen/CMakeLists.txt
utils/TableGen/RegisterBankEmitter.cpp [new file with mode: 0644]
utils/TableGen/TableGen.cpp
utils/TableGen/TableGenBackends.h