]> granicus.if.org Git - llvm/commit
Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake
authorLuo, Yuanke <yuanke.luo@intel.com>
Mon, 6 May 2019 08:22:37 +0000 (08:22 +0000)
committerLuo, Yuanke <yuanke.luo@intel.com>
Mon, 6 May 2019 08:22:37 +0000 (08:22 +0000)
commit0e258a059f068bee0445c6186ef40beceffbb64d
treeea3629e5c4178b2ac9aeaabe5d2f117672e7f614
parent0d9a164240ed293701eea6af0ea338caf227c338
Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake

Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS  instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data.
VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data.
VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

Author: LiuTianle

Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, RKSimon, spatel

Reviewed By: craig.topper

Subscribers: kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60550

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360017 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsX86.td
lib/Support/Host.cpp
lib/Target/X86/X86.td
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86InstrInfo.td
lib/Target/X86/X86IntrinsicsInfo.h
lib/Target/X86/X86Subtarget.h