]> granicus.if.org Git - llvm/commit
[X86] Add test case to show missed opportunity to remove an explicit AND on the bit...
authorCraig Topper <craig.topper@intel.com>
Wed, 20 Feb 2019 19:02:01 +0000 (19:02 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 20 Feb 2019 19:02:01 +0000 (19:02 +0000)
commit0d757236edb02e16e43a1f1dc0e3427227f0197b
treeeb9958de143cc9c8835d9d39723e0c51000ca544
parent9bba64895e8550db021be6ad76eaba9f352e01ca
[X86] Add test case to show missed opportunity to remove an explicit AND on the bit position from BT when it has known zeros. NFC

If the bit position has known zeros in it, then the AND immediate will likely be optimized to remove bits.

This can prevent GetDemandedBits from recognizing that the AND is unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354501 91177308-0d34-0410-b5e6-96231b3b80d8
test/CodeGen/X86/bt.ll