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[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model
authorCraig Topper <craig.topper@intel.com>
Thu, 7 Mar 2019 21:22:51 +0000 (21:22 +0000)
committerCraig Topper <craig.topper@intel.com>
Thu, 7 Mar 2019 21:22:51 +0000 (21:22 +0000)
commit0d2610da268833fdca95d80d2134d81f546eb854
tree547724e9602f4fb328d3b08780cc5783c9e1f054tree | snapshot
parent1c4b1cfc76f80af6d090caa4a411fbbbaf065ffbcommit | diff
[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model

Haswell and possibly Sandybridge have an optimization for ADC/SBB with immediate 0 to use a single uop flow. This only applies GR16/GR32/GR64 with an 8-bit immediate. It does not apply to GR8. It also does not apply to the implicit AX/EAX/RAX forms.

Differential Revision: https://reviews.llvm.org/D59058

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355635 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86SchedHaswell.td diff | blob | history
test/tools/llvm-mca/X86/Haswell/resources-x86_64.s diff | blob | history
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