]> granicus.if.org Git - llvm/commit
[InstCombine] add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1
authorSanjay Patel <spatel@rotateright.com>
Wed, 10 May 2017 13:56:52 +0000 (13:56 +0000)
committerSanjay Patel <spatel@rotateright.com>
Wed, 10 May 2017 13:56:52 +0000 (13:56 +0000)
commit0cf1e1c3185d21b217529037b90d8a008e1c3b63
tree5526fd2ae0b29972ab2fa279b02974df45c65199
parent2490292bed01d4283d3c5a85f1a4ea368f2effee
[InstCombine] add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1

This is another step towards favoring 'not' ops over random 'xor' in IR:
https://bugs.llvm.org/show_bug.cgi?id=32706

This transformation may have occurred in longer IR sequences using computeKnownBits,
but that could be much more expensive to calculate.

As the scalar result shows, we do not currently favor 'not' in all cases. The 'not'
created by the transform is transformed again (unnecessarily). Vectors don't have
this problem because vectors are (wrongly) excluded from several other combines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302659 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineAddSub.cpp
test/Transforms/InstCombine/add.ll