]> granicus.if.org Git - llvm/commit
[X86][SSE] Improve bool vector extload (PR26091)
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 30 May 2019 10:25:20 +0000 (10:25 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 30 May 2019 10:25:20 +0000 (10:25 +0000)
commit0ce7855c987db4fe9c69a674d0e9f73dcbb8db7c
tree472049ccf21341b7132410e5e7ca3164279eea88
parent10450cbfe6fe4106f6bcfddcb8c62aa0d8462396
[X86][SSE] Improve bool vector extload (PR26091)

We already have good codegen for (vXiY *ext(vXi1 bitcast(iX))) cases, this patch uses it for loads of vXi1 types as well - changing the load into a iX integer load, and bitcasting so that combineToExtendBoolVectorInReg can then use it.

Differential Revision: https://reviews.llvm.org/D62449

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362081 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/vector-sext-widen.ll
test/CodeGen/X86/vector-sext.ll