]> granicus.if.org Git - llvm/commit
Merging r266152:
authorTom Stellard <thomas.stellard@amd.com>
Fri, 3 Jun 2016 20:48:40 +0000 (20:48 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Fri, 3 Jun 2016 20:48:40 +0000 (20:48 +0000)
commit0afb7d7e714023374af9142545688ece2b8c6e67
tree2e3ba8ac6b99e143755e62ed330e4621e923cf5f
parent751b64f18ef927a5cfd824958e86af62bbe98221
Merging r266152:

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r266152 | thomas.stellard | 2016-04-12 16:57:30 -0700 (Tue, 12 Apr 2016) | 13 lines

AMDGPU/SI: Fix spilling of 96-bit registers

Summary:
It seems like this was broken in r252327.  I thought we had test cases
for this, but it's really hard to tirgger spills of this exact register
size since they aren't used very much.

Reviewers: arsenm, nhaehnle

Subscribers: nhaehnle, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19021

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271735 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SIInstrInfo.cpp