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R600/SI: Fix bug in VGPR spilling
authorTom Stellard <thomas.stellard@amd.com>
Tue, 12 May 2015 18:59:17 +0000 (18:59 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Tue, 12 May 2015 18:59:17 +0000 (18:59 +0000)
commit07cf3c32e3d621afd3c3541db76f467a75abf86b
tree19787c1d67b9181e3bb255365102bc633f64fb5etree | snapshot
parenteaba2dd2f13a53fd148ccd41c27214c147b958b0commit | diff
R600/SI: Fix bug in VGPR spilling

AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which
caused the srsrc and soffset register to not be set correctly.

This commit replaces the switch statement with a SITargetInfo query
to make sure all spill instructions are covered.

Differential Revision: http://reviews.llvm.org/D9582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237164 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/SIDefines.h diff | blob | history
lib/Target/R600/SIInstrFormats.td diff | blob | history
lib/Target/R600/SIInstrInfo.h diff | blob | history
lib/Target/R600/SIInstructions.td diff | blob | history
lib/Target/R600/SIPrepareScratchRegs.cpp diff | blob | history
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