[x86] vectorize cast ops in lowering to avoid register file transfers

[x86] vectorize cast ops in lowering to avoid register file transfers

The proposal in D56796 may cross the line because we're trying to avoid vectorization
transforms in generic DAG combining. So this is an alternate, later, x86-specific
translation of that patch.

There are several potential follow-ups to enhance this:
1. Allow extraction from non-zero element index.
2. Peek through extends of smaller width integers.
3. Support x86-specific conversion opcodes like X86ISD::CVTSI2P

Differential Revision: https://reviews.llvm.org/D56864

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353302 91177308-0d34-0410-b5e6-96231b3b80d8