* Tests if the lock is free. Returns TRUE if free, FALSE if locked.
* This does *not* change the state of the lock.
*
+ * void SPIN_DELAY(void)
+ * Delay operation to occur inside spinlock wait loop.
+ *
* Note to implementors: there are default implementations for all these
* macros at the bottom of the file. Check if your platform can use
* these or needs to override them.
* in assembly language to execute a hardware atomic-test-and-set
* instruction. Equivalent OS-supplied mutex routines could be used too.
*
- * If no system-specific TAS() is available (ie, HAS_TEST_AND_SET is not
+ * If no system-specific TAS() is available (ie, HAVE_SPINLOCKS is not
* defined), then we fall back on an emulation that uses SysV semaphores
* (see spin.c). This emulation will be MUCH MUCH slower than a proper TAS()
* implementation, because of the cost of a kernel call per lock or unlock.
* when using the SysV semaphore code.
*
*
- * Portions Copyright (c) 1996-2003, PostgreSQL Global Development Group
+ * Portions Copyright (c) 1996-2005, PostgreSQL Global Development Group
* Portions Copyright (c) 1994, Regents of the University of California
*
- * $PostgreSQL: pgsql/src/include/storage/s_lock.h,v 1.121 2003/12/23 03:52:10 momjian Exp $
+ * $PostgreSQL: pgsql/src/include/storage/s_lock.h,v 1.134 2005/03/10 21:41:01 momjian Exp $
*
*-------------------------------------------------------------------------
*/
#ifdef HAVE_SPINLOCKS /* skip spinlocks if requested */
+
#if defined(__GNUC__) || defined(__ICC)
/*************************************************************************
* All the gcc inlines
* Other compilers use __cpu or __cpu__ so we test for both in those cases.
*/
-/*
- * Standard gcc asm format:
- *
+/*----------
+ * Standard gcc asm format (assuming "volatile slock_t *lock"):
+
__asm__ __volatile__(
- " command \n"
- " command \n"
- " command \n"
-: "=r"(_res) return value, in register
-: "r"(lock) argument, 'lock pointer', in register
-: "r0"); inline code uses this register
+ " instruction \n"
+ " instruction \n"
+ " instruction \n"
+: "=r"(_res), "+m"(*lock) // return register, in/out lock value
+: "r"(lock) // lock pointer, in input register
+: "memory", "cc"); // show clobbered registers here
+
+ * The output-operands list (after first colon) should always include
+ * "+m"(*lock), whether or not the asm code actually refers to this
+ * operand directly. This ensures that gcc believes the value in the
+ * lock variable is used and set by the asm code. Also, the clobbers
+ * list (after third colon) should always include "memory"; this prevents
+ * gcc from thinking it can cache the values of shared-memory fields
+ * across the asm code. Add "cc" if your asm code changes the condition
+ * code register, and also list any temp registers the code uses.
+ *----------
*/
#if defined(__i386__) || defined(__x86_64__) /* AMD Opteron */
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+typedef unsigned char slock_t;
+
#define TAS(lock) tas(lock)
static __inline__ int
{
register slock_t _res = 1;
+ /* Use a non-locking test before asserting the bus lock */
__asm__ __volatile__(
+ " cmpb $0,%1 \n"
+ " jne 1f \n"
" lock \n"
" xchgb %0,%1 \n"
-: "=q"(_res), "=m"(*lock)
-: "0"(_res));
+ "1: \n"
+: "+q"(_res), "+m"(*lock)
+:
+: "memory", "cc");
return (int) _res;
}
+#define SPIN_DELAY() spin_delay()
+
+static __inline__ void
+spin_delay(void)
+{
+ /*
+ * This sequence is equivalent to the PAUSE instruction ("rep" is
+ * ignored by old IA32 processors if the following instruction is
+ * not a string operation); the IA-32 Architecture Software
+ * Developer's Manual, Vol. 3, Section 7.7.2 describes why using
+ * PAUSE in the inner loop of a spin lock is necessary for good
+ * performance:
+ *
+ * The PAUSE instruction improves the performance of IA-32
+ * processors supporting Hyper-Threading Technology when
+ * executing spin-wait loops and other routines where one
+ * thread is accessing a shared lock or semaphore in a tight
+ * polling loop. When executing a spin-wait loop, the
+ * processor can suffer a severe performance penalty when
+ * exiting the loop because it detects a possible memory order
+ * violation and flushes the core processor's pipeline. The
+ * PAUSE instruction provides a hint to the processor that the
+ * code sequence is a spin-wait loop. The processor uses this
+ * hint to avoid the memory order violation and prevent the
+ * pipeline flush. In addition, the PAUSE instruction
+ * de-pipelines the spin-wait loop to prevent it from
+ * consuming execution resources excessively.
+ */
+ __asm__ __volatile__(
+ " rep; nop \n");
+}
+
#endif /* __i386__ || __x86_64__ */
+#if defined(__ia64__) || defined(__ia64)
/* Intel Itanium */
-#if defined(__ia64__) || defined(__ia64) /* __ia64 is used by ICC the compiler? */
-typedef unsigned int slock_t;
#define HAS_TEST_AND_SET
+typedef unsigned int slock_t;
+
#define TAS(lock) tas(lock)
+#ifndef __INTEL_COMPILER
+
static __inline__ int
tas(volatile slock_t *lock)
{
__asm__ __volatile__(
" xchg4 %0=%1,%2 \n"
-: "=r"(ret), "=m"(*lock)
-: "r"(1), "1"(*lock)
+: "=r"(ret), "+m"(*lock)
+: "r"(1)
: "memory");
-
return (int) ret;
}
+#else
+
+static __inline__ int
+tas(volatile slock_t *lock)
+{
+ int ret;
+
+ ret = _InterlockedExchange(lock,1); /* this is a xchg asm macro */
+
+ return ret;
+}
+
+#endif
#endif /* __ia64__ || __ia64 */
#if defined(__arm__) || defined(__arm)
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+typedef unsigned char slock_t;
+
#define TAS(lock) tas(lock)
static __inline__ int
register slock_t _res = 1;
__asm__ __volatile__(
- " swpb %0, %0, [%3] \n"
-: "=r"(_res), "=m"(*lock)
-: "0"(_res), "r"(lock));
+ " swpb %0, %0, [%2] \n"
+: "+r"(_res), "+m"(*lock)
+: "r"(lock)
+: "memory");
return (int) _res;
}
#endif /* __arm__ */
-#if defined(__s390__) && !defined(__s390x__)
-typedef unsigned int slock_t;
+#if defined(__s390__) || defined(__s390x__)
+/* S/390 and S/390x Linux (32- and 64-bit zSeries) */
#define HAS_TEST_AND_SET
-/* S/390 Linux */
-#define TAS(lock) tas(lock)
-
-static __inline__ int
-tas(volatile slock_t *lock)
-{
- int _res;
-
- __asm__ __volatile__(
- " la 1,1 \n"
- " l 2,%2 \n"
- " slr 0,0 \n"
- " cs 0,1,0(2) \n"
- " lr %1,0 \n"
-: "=m"(lock), "=d"(_res)
-: "m"(lock)
-: "0", "1", "2");
-
- return (_res);
-}
-
-#endif /* __s390__ */
-
-#if defined(__s390x__)
typedef unsigned int slock_t;
-#define HAS_TEST_AND_SET
-/* S/390x Linux (64-bit zSeries) */
+
#define TAS(lock) tas(lock)
static __inline__ int
tas(volatile slock_t *lock)
{
- int _res;
+ int _res = 0;
__asm__ __volatile__(
- " la 1,1 \n"
- " lg 2,%2 \n"
- " slr 0,0 \n"
- " cs 0,1,0(2) \n"
- " lr %1,0 \n"
-: "=m"(lock), "=d"(_res)
-: "m"(lock)
-: "0", "1", "2");
-
- return (_res);
+ " cs %0,%3,0(%2) \n"
+: "+d"(_res), "+m"(*lock)
+: "a"(lock), "d"(1)
+: "memory", "cc");
+ return _res;
}
-#endif /* __s390x__ */
+#endif /* __s390__ || __s390x__ */
#if defined(__sparc__)
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
#define TAS(lock) tas(lock)
static __inline__ int
tas(volatile slock_t *lock)
{
- register slock_t _res = 1;
+ register slock_t _res;
__asm__ __volatile__(
" ldstub [%2], %0 \n"
-: "=r"(_res), "=m"(*lock)
-: "r"(lock));
+: "=r"(_res), "+m"(*lock)
+: "r"(lock)
+: "memory");
return (int) _res;
}
#endif /* __sparc__ */
+
#if defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__)
-/* Is this correct? */
-#ifndef defined(__powerpc64__)
-typedef unsigned int slock_t;
-#else
+#define HAS_TEST_AND_SET
+
+#if defined(__powerpc64__)
typedef unsigned long slock_t;
+#else
+typedef unsigned int slock_t;
#endif
-#define HAS_TEST_AND_SET
#define TAS(lock) tas(lock)
/*
int _res;
__asm__ __volatile__(
-" lwarx %0,0,%2 \n"
+" lwarx %0,0,%3 \n"
" cmpwi %0,0 \n"
" bne 1f \n"
" addi %0,%0,1 \n"
-" stwcx. %0,0,%2 \n"
+" stwcx. %0,0,%3 \n"
" beq 2f \n"
"1: li %1,1 \n"
" b 3f \n"
" li %1,0 \n"
"3: \n"
-: "=&r" (_t), "=r" (_res)
-: "r" (lock)
-: "cc", "memory"
- );
+: "=&r"(_t), "=r"(_res), "+m"(*lock)
+: "r"(lock)
+: "memory", "cc");
return _res;
}
-/*
- * PowerPC S_UNLOCK is almost standard but requires a "sync" instruction.
- */
+/* PowerPC S_UNLOCK is almost standard but requires a "sync" instruction */
#define S_UNLOCK(lock) \
do \
{\
#if defined(__mc68000__) && defined(__linux__)
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
#define TAS(lock) tas(lock)
static __inline__ int
" clrl %0 \n"
" tas %1 \n"
" sne %0 \n"
-: "=d"(rv), "=m"(*lock)
-: "1"(*lock)
-: "cc");
-
+: "=d"(rv), "+m"(*lock)
+:
+: "memory", "cc");
return rv;
}
* VAXen -- even multiprocessor ones
* (thanks to Tom Ivar Helbekkmo)
*/
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
#define TAS(lock) tas(lock)
static __inline__ int
register int _res;
__asm__ __volatile__(
- " movl $1, r0 \n"
- " bbssi $0, (%1), 1f \n"
- " clrl r0 \n"
- "1: movl r0, %0 \n"
-: "=r"(_res)
+ " movl $1, %0 \n"
+ " bbssi $0, (%2), 1f \n"
+ " clrl %0 \n"
+ "1: \n"
+: "=&r"(_res), "+m"(*lock)
: "r"(lock)
-: "r0");
+: "memory");
return _res;
}
#if defined(__ns32k__)
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
#define TAS(lock) tas(lock)
static __inline__ int
register int _res;
__asm__ __volatile__(
- " sbitb 0, %0 \n"
- " sfsd %1 \n"
-: "=m"(*lock), "=r"(_res));
+ " sbitb 0, %1 \n"
+ " sfsd %0 \n"
+: "=r"(_res), "+m"(*lock)
+:
+: "memory");
return _res;
}
* found at ftp://ftp.netbsd.org/pub/NetBSD/misc/dec-docs/index.html.
* For gcc we implement the handbook's code directly with inline assembler.
*/
-typedef unsigned long slock_t;
#define HAS_TEST_AND_SET
+typedef unsigned long slock_t;
+
#define TAS(lock) tas(lock)
-#define S_UNLOCK(lock) \
-do \
-{\
- __asm__ __volatile__ (" mb \n"); \
- *((volatile slock_t *) (lock)) = 0; \
-} while (0)
static __inline__ int
tas(volatile slock_t *lock)
register slock_t _res;
__asm__ __volatile__(
- " ldq $0, %0 \n"
+ " ldq $0, %1 \n"
" bne $0, 2f \n"
- " ldq_l %1, %0 \n"
- " bne %1, 2f \n"
+ " ldq_l %0, %1 \n"
+ " bne %0, 2f \n"
" mov 1, $0 \n"
- " stq_c $0, %0 \n"
+ " stq_c $0, %1 \n"
" beq $0, 2f \n"
" mb \n"
" br 3f \n"
- "2: mov 1, %1 \n"
+ "2: mov 1, %0 \n"
"3: \n"
-: "=m"(*lock), "=r"(_res)
+: "=&r"(_res), "+m"(*lock)
:
-: "0");
-
+: "memory", "0");
return (int) _res;
}
+#define S_UNLOCK(lock) \
+do \
+{\
+ __asm__ __volatile__ (" mb \n"); \
+ *((volatile slock_t *) (lock)) = 0; \
+} while (0)
+
#endif /* __alpha || __alpha__ */
/* These live in s_lock.c, but only for gcc */
-#if defined(__m68k__)
-typedef unsigned char slock_t;
-#define HAS_TEST_AND_SET
-#endif
-#ifdef sinix /* This symbol is not protected with __, for SvR4 port */
-#include "abi_mutex.h"
-typedef abilock_t slock_t;
+#if defined(__m68k__)
#define HAS_TEST_AND_SET
-#endif
-
-/* These are in s_lock.c */
-
-#if defined(__m68k__)
typedef unsigned char slock_t;
-#define HAS_TEST_AND_SET
#endif
+
#if defined(__mips__) && !defined(__sgi)
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned int slock_t;
#endif
+
#endif /* __GNUC__ */
/***************************************************************************
- * Uses non-gcc inline assembly:
+ * Platforms that use non-gcc inline assembly:
*/
#if !defined(HAS_TEST_AND_SET) /* We didn't trigger above, let's try here */
+
#if defined(USE_UNIVEL_CC)
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
#define TAS(lock) tas(lock)
asm int
#if defined(__alpha) || defined(__alpha__)
-typedef volatile long slock_t;
-#define HAS_TEST_AND_SET
/*
* The Tru64 compiler doesn't support gcc-style inline asm, but it does
* have some builtin functions that accomplish much the same results.
* operate on an int (ie, longword), but that's OK as long as we define
* S_INIT_LOCK to zero out the whole quadword.
*/
+#define HAS_TEST_AND_SET
+
+typedef unsigned long slock_t;
#include <alpha/builtins.h>
#define S_INIT_LOCK(lock) (*(lock) = 0)
#endif /* __alpha || __alpha__ */
-#if defined(__hppa)
-typedef struct
-{
- int sema[4];
-} slock_t;
-#define HAS_TEST_AND_SET
+#if defined(__hppa) || defined(__hppa__)
/*
* HP's PA-RISC
*
- * Note that slock_t on PA-RISC is a structure instead of char
- * (see include/port/hpux.h).
+ * See src/backend/port/hpux/tas.c.template for details about LDCWX. Because
+ * LDCWX requires a 16-byte-aligned address, we declare slock_t as a 16-byte
+ * struct. The active word in the struct is whichever has the aligned address;
+ * the other three words just sit at -1.
*
- * a "set" slock_t has a single word cleared. a "clear" slock_t has
- * all words set to non-zero. tas() is in tas.s
+ * When using gcc, we can inline the required assembly code.
*/
+#define HAS_TEST_AND_SET
-#define S_UNLOCK(lock) \
+typedef struct
+{
+ int sema[4];
+} slock_t;
+
+#define TAS_ACTIVE_WORD(lock) ((volatile int *) (((long) (lock) + 15) & ~15))
+
+#if defined(__GNUC__)
+
+static __inline__ int
+tas(volatile slock_t *lock)
+{
+ volatile int *lockword = TAS_ACTIVE_WORD(lock);
+ register int lockval;
+
+ __asm__ __volatile__(
+ " ldcwx 0(0,%2),%0 \n"
+: "=r"(lockval), "+m"(*lockword)
+: "r"(lockword)
+: "memory");
+ return (lockval == 0);
+}
+
+#endif /* __GNUC__ */
+
+#define S_UNLOCK(lock) (*TAS_ACTIVE_WORD(lock) = -1)
+
+#define S_INIT_LOCK(lock) \
do { \
- volatile slock_t *lock_ = (volatile slock_t *) (lock); \
+ volatile slock_t *lock_ = (lock); \
lock_->sema[0] = -1; \
lock_->sema[1] = -1; \
lock_->sema[2] = -1; \
lock_->sema[3] = -1; \
} while (0)
-#define S_LOCK_FREE(lock) ( *(int *) (((long) (lock) + 15) & ~15) != 0)
+#define S_LOCK_FREE(lock) (*TAS_ACTIVE_WORD(lock) != 0)
-#endif /* __hppa */
+#endif /* __hppa || __hppa__ */
-#if defined(__QNX__) && defined(__WATCOMC__)
-typedef unsigned char slock_t;
+#if defined(__hpux) && defined(__ia64) && !defined(__GNUC__)
+
#define HAS_TEST_AND_SET
+
+typedef unsigned int slock_t;
+
+#include <ia64/sys/inline.h>
+#define TAS(lock) _Asm_xchg(_SZ_W, lock, 1, _LDHINT_NONE)
+
+#endif /* HPUX on IA64, non gcc */
+
+
+#if defined(__QNX__) && defined(__WATCOMC__)
/*
* QNX 4 using WATCOM C
*/
+#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+
#define TAS(lock) wc_tas(lock)
extern slock_t wc_tas(volatile slock_t *lock);
#pragma aux wc_tas =\
* assembly from his NECEWS SVR4 port, but we probably ought to retain this
* for the R3000 chips out there.
*/
-typedef unsigned long slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned long slock_t;
+
#include "mutex.h"
#define TAS(lock) (test_and_set(lock,1))
#define S_UNLOCK(lock) (test_then_and(lock,0))
* SINIX / Reliant UNIX
* slock_t is defined as a struct abilock_t, which has a single unsigned long
* member. (Basically same as SGI)
- *
*/
#define HAS_TEST_AND_SET
+
+#include "abi_mutex.h"
+typedef abilock_t slock_t;
+
#define TAS(lock) (!acquire_lock(lock))
#define S_UNLOCK(lock) release_lock(lock)
#define S_INIT_LOCK(lock) init_lock(lock)
#if defined(_AIX)
/*
* AIX (POWER)
- *
- * Note that slock_t on POWER/POWER2/PowerPC is int instead of char
*/
#define HAS_TEST_AND_SET
+
+typedef unsigned int slock_t;
+
#define TAS(lock) _check_lock(lock, 0, 1)
#define S_UNLOCK(lock) _clear_lock(lock, 0)
#endif /* _AIX */
#if defined (nextstep)
-typedef struct mutex slock_t;
#define HAS_TEST_AND_SET
+typedef struct mutex slock_t;
+
#define S_LOCK(lock) mutex_lock(lock)
#define S_UNLOCK(lock) mutex_unlock(lock)
#define S_INIT_LOCK(lock) mutex_init(lock)
#define S_LOCK_FREE(alock) ((alock)->lock == 0)
#endif /* nextstep */
+
/* These are in s_lock.c */
+
#if defined(sun3)
-typedef unsigned char slock_t;
#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
#endif
+
#if defined(__sparc__) || defined(__sparc)
#define HAS_TEST_AND_SET
+
typedef unsigned char slock_t;
#endif
-#endif /* !defined(HAS_TEST_AND_SET */
+/* out-of-line assembler from src/backend/port/tas/foo.s */
-#endif /* HAVE_SPINLOCKS */
+#if defined(__sun) && defined(__i386)
+/*
+ * Solaris/386 (we only get here for non-gcc case)
+ */
+#define HAS_TEST_AND_SET
+
+typedef unsigned char slock_t;
+#endif
+#endif /* !defined(HAS_TEST_AND_SET) */
+
+
+/* Blow up if we didn't have any way to do spinlocks */
#ifndef HAS_TEST_AND_SET
-#ifdef HAVE_SPINLOCKS
#error PostgreSQL does not have native spinlock support on this platform. To continue the compilation, rerun configure using --disable-spinlocks. However, performance will be poor. Please report this to pgsql-bugs@postgresql.org.
+#endif
+
+
+#else /* !HAVE_SPINLOCKS */
-#else
/*
* Fake spinlock implementation using semaphores --- slow and prone
#define S_INIT_LOCK(lock) s_init_lock_sema(lock)
#define TAS(lock) tas_sema(lock)
-#endif /* HAVE_SPINLOCKS */
-#endif /* HAS_TEST_AND_SET */
+#endif /* HAVE_SPINLOCKS */
/*
#define S_INIT_LOCK(lock) S_UNLOCK(lock)
#endif /* S_INIT_LOCK */
+#if !defined(SPIN_DELAY)
+#define SPIN_DELAY() ((void) 0)
+#endif /* SPIN_DELAY */
+
#if !defined(TAS)
extern int tas(volatile slock_t *lock); /* in port/.../tas.s, or
* s_lock.c */
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