+#elif defined(TILE)
+ { PTREGS_OFFSET_REG(0), "r0" },
+ { PTREGS_OFFSET_REG(1), "r1" },
+ { PTREGS_OFFSET_REG(2), "r2" },
+ { PTREGS_OFFSET_REG(3), "r3" },
+ { PTREGS_OFFSET_REG(4), "r4" },
+ { PTREGS_OFFSET_REG(5), "r5" },
+ { PTREGS_OFFSET_REG(6), "r6" },
+ { PTREGS_OFFSET_REG(7), "r7" },
+ { PTREGS_OFFSET_REG(8), "r8" },
+ { PTREGS_OFFSET_REG(9), "r9" },
+ { PTREGS_OFFSET_REG(10), "r10" },
+ { PTREGS_OFFSET_REG(11), "r11" },
+ { PTREGS_OFFSET_REG(12), "r12" },
+ { PTREGS_OFFSET_REG(13), "r13" },
+ { PTREGS_OFFSET_REG(14), "r14" },
+ { PTREGS_OFFSET_REG(15), "r15" },
+ { PTREGS_OFFSET_REG(16), "r16" },
+ { PTREGS_OFFSET_REG(17), "r17" },
+ { PTREGS_OFFSET_REG(18), "r18" },
+ { PTREGS_OFFSET_REG(19), "r19" },
+ { PTREGS_OFFSET_REG(20), "r20" },
+ { PTREGS_OFFSET_REG(21), "r21" },
+ { PTREGS_OFFSET_REG(22), "r22" },
+ { PTREGS_OFFSET_REG(23), "r23" },
+ { PTREGS_OFFSET_REG(24), "r24" },
+ { PTREGS_OFFSET_REG(25), "r25" },
+ { PTREGS_OFFSET_REG(26), "r26" },
+ { PTREGS_OFFSET_REG(27), "r27" },
+ { PTREGS_OFFSET_REG(28), "r28" },
+ { PTREGS_OFFSET_REG(29), "r29" },
+ { PTREGS_OFFSET_REG(30), "r30" },
+ { PTREGS_OFFSET_REG(31), "r31" },
+ { PTREGS_OFFSET_REG(32), "r32" },
+ { PTREGS_OFFSET_REG(33), "r33" },
+ { PTREGS_OFFSET_REG(34), "r34" },
+ { PTREGS_OFFSET_REG(35), "r35" },
+ { PTREGS_OFFSET_REG(36), "r36" },
+ { PTREGS_OFFSET_REG(37), "r37" },
+ { PTREGS_OFFSET_REG(38), "r38" },
+ { PTREGS_OFFSET_REG(39), "r39" },
+ { PTREGS_OFFSET_REG(40), "r40" },
+ { PTREGS_OFFSET_REG(41), "r41" },
+ { PTREGS_OFFSET_REG(42), "r42" },
+ { PTREGS_OFFSET_REG(43), "r43" },
+ { PTREGS_OFFSET_REG(44), "r44" },
+ { PTREGS_OFFSET_REG(45), "r45" },
+ { PTREGS_OFFSET_REG(46), "r46" },
+ { PTREGS_OFFSET_REG(47), "r47" },
+ { PTREGS_OFFSET_REG(48), "r48" },
+ { PTREGS_OFFSET_REG(49), "r49" },
+ { PTREGS_OFFSET_REG(50), "r50" },
+ { PTREGS_OFFSET_REG(51), "r51" },
+ { PTREGS_OFFSET_REG(52), "r52" },
+ { PTREGS_OFFSET_TP, "tp" },
+ { PTREGS_OFFSET_SP, "sp" },
+ { PTREGS_OFFSET_LR, "lr" },
+ { PTREGS_OFFSET_PC, "pc" },
+ { PTREGS_OFFSET_EX1, "ex1" },
+ { PTREGS_OFFSET_FAULTNUM, "faultnum" },
+ { PTREGS_OFFSET_ORIG_R0, "orig_r0" },
+ { PTREGS_OFFSET_FLAGS, "flags" },
+#endif
+#ifdef CRISV10
+ { 4*PT_FRAMETYPE, "4*PT_FRAMETYPE" },
+ { 4*PT_ORIG_R10, "4*PT_ORIG_R10" },
+ { 4*PT_R13, "4*PT_R13" },
+ { 4*PT_R12, "4*PT_R12" },
+ { 4*PT_R11, "4*PT_R11" },
+ { 4*PT_R10, "4*PT_R10" },
+ { 4*PT_R9, "4*PT_R9" },
+ { 4*PT_R8, "4*PT_R8" },
+ { 4*PT_R7, "4*PT_R7" },
+ { 4*PT_R6, "4*PT_R6" },
+ { 4*PT_R5, "4*PT_R5" },
+ { 4*PT_R4, "4*PT_R4" },
+ { 4*PT_R3, "4*PT_R3" },
+ { 4*PT_R2, "4*PT_R2" },
+ { 4*PT_R1, "4*PT_R1" },
+ { 4*PT_R0, "4*PT_R0" },
+ { 4*PT_MOF, "4*PT_MOF" },
+ { 4*PT_DCCR, "4*PT_DCCR" },
+ { 4*PT_SRP, "4*PT_SRP" },
+ { 4*PT_IRP, "4*PT_IRP" },
+ { 4*PT_CSRINSTR, "4*PT_CSRINSTR" },
+ { 4*PT_CSRADDR, "4*PT_CSRADDR" },
+ { 4*PT_CSRDATA, "4*PT_CSRDATA" },
+ { 4*PT_USP, "4*PT_USP" },
+#endif
+#ifdef CRISV32
+ { 4*PT_ORIG_R10, "4*PT_ORIG_R10" },
+ { 4*PT_R0, "4*PT_R0" },
+ { 4*PT_R1, "4*PT_R1" },
+ { 4*PT_R2, "4*PT_R2" },
+ { 4*PT_R3, "4*PT_R3" },
+ { 4*PT_R4, "4*PT_R4" },
+ { 4*PT_R5, "4*PT_R5" },
+ { 4*PT_R6, "4*PT_R6" },
+ { 4*PT_R7, "4*PT_R7" },
+ { 4*PT_R8, "4*PT_R8" },
+ { 4*PT_R9, "4*PT_R9" },
+ { 4*PT_R10, "4*PT_R10" },
+ { 4*PT_R11, "4*PT_R11" },
+ { 4*PT_R12, "4*PT_R12" },
+ { 4*PT_R13, "4*PT_R13" },
+ { 4*PT_ACR, "4*PT_ACR" },
+ { 4*PT_SRS, "4*PT_SRS" },
+ { 4*PT_MOF, "4*PT_MOF" },
+ { 4*PT_SPC, "4*PT_SPC" },
+ { 4*PT_CCS, "4*PT_CCS" },
+ { 4*PT_SRP, "4*PT_SRP" },
+ { 4*PT_ERP, "4*PT_ERP" },
+ { 4*PT_EXS, "4*PT_EXS" },
+ { 4*PT_EDA, "4*PT_EDA" },
+ { 4*PT_USP, "4*PT_USP" },
+ { 4*PT_PPC, "4*PT_PPC" },
+ { 4*PT_BP_CTRL, "4*PT_BP_CTRL" },
+ { 4*PT_BP+4, "4*PT_BP+4" },
+ { 4*PT_BP+8, "4*PT_BP+8" },
+ { 4*PT_BP+12, "4*PT_BP+12" },
+ { 4*PT_BP+16, "4*PT_BP+16" },
+ { 4*PT_BP+20, "4*PT_BP+20" },
+ { 4*PT_BP+24, "4*PT_BP+24" },
+ { 4*PT_BP+28, "4*PT_BP+28" },
+ { 4*PT_BP+32, "4*PT_BP+32" },
+ { 4*PT_BP+36, "4*PT_BP+36" },
+ { 4*PT_BP+40, "4*PT_BP+40" },
+ { 4*PT_BP+44, "4*PT_BP+44" },
+ { 4*PT_BP+48, "4*PT_BP+48" },
+ { 4*PT_BP+52, "4*PT_BP+52" },
+ { 4*PT_BP+56, "4*PT_BP+56" },
+#endif
+#ifdef MICROBLAZE
+ { PT_GPR(0), "r0" },
+ { PT_GPR(1), "r1" },
+ { PT_GPR(2), "r2" },
+ { PT_GPR(3), "r3" },
+ { PT_GPR(4), "r4" },
+ { PT_GPR(5), "r5" },
+ { PT_GPR(6), "r6" },
+ { PT_GPR(7), "r7" },
+ { PT_GPR(8), "r8" },
+ { PT_GPR(9), "r9" },
+ { PT_GPR(10), "r10" },
+ { PT_GPR(11), "r11" },
+ { PT_GPR(12), "r12" },
+ { PT_GPR(13), "r13" },
+ { PT_GPR(14), "r14" },
+ { PT_GPR(15), "r15" },
+ { PT_GPR(16), "r16" },
+ { PT_GPR(17), "r17" },
+ { PT_GPR(18), "r18" },
+ { PT_GPR(19), "r19" },
+ { PT_GPR(20), "r20" },
+ { PT_GPR(21), "r21" },
+ { PT_GPR(22), "r22" },
+ { PT_GPR(23), "r23" },
+ { PT_GPR(24), "r24" },
+ { PT_GPR(25), "r25" },
+ { PT_GPR(26), "r26" },
+ { PT_GPR(27), "r27" },
+ { PT_GPR(28), "r28" },
+ { PT_GPR(29), "r29" },
+ { PT_GPR(30), "r30" },
+ { PT_GPR(31), "r31" },
+ { PT_PC, "rpc", },
+ { PT_MSR, "rmsr", },
+ { PT_EAR, "rear", },
+ { PT_ESR, "resr", },
+ { PT_FSR, "rfsr", },
+ { PT_KERNEL_MODE, "kernel_mode", },
+#endif
+#ifdef OR1K
+ { 4*0, "r0" },
+ { 4*1, "r1" },
+ { 4*2, "r2" },
+ { 4*3, "r3" },
+ { 4*4, "r4" },
+ { 4*5, "r5" },
+ { 4*6, "r6" },
+ { 4*7, "r7" },
+ { 4*8, "r8" },
+ { 4*9, "r9" },
+ { 4*10, "r10" },
+ { 4*11, "r11" },
+ { 4*12, "r12" },
+ { 4*13, "r13" },
+ { 4*14, "r14" },
+ { 4*15, "r15" },
+ { 4*16, "r16" },
+ { 4*17, "r17" },
+ { 4*18, "r18" },
+ { 4*19, "r19" },
+ { 4*20, "r20" },
+ { 4*21, "r21" },
+ { 4*22, "r22" },
+ { 4*23, "r23" },
+ { 4*24, "r24" },
+ { 4*25, "r25" },
+ { 4*26, "r26" },
+ { 4*27, "r27" },
+ { 4*28, "r28" },
+ { 4*29, "r29" },
+ { 4*30, "r30" },
+ { 4*31, "r31" },
+ { 4*32, "pc" },
+ { 4*33, "sr" },
+#endif
+#ifdef XTENSA
+ { SYSCALL_NR, "syscall_nr" },
+ { REG_AR_BASE, "ar0" },
+ { REG_AR_BASE+1, "ar1" },
+ { REG_AR_BASE+2, "ar2" },
+ { REG_AR_BASE+3, "ar3" },
+ { REG_AR_BASE+4, "ar4" },
+ { REG_AR_BASE+5, "ar5" },
+ { REG_AR_BASE+6, "ar6" },
+ { REG_AR_BASE+7, "ar7" },
+ { REG_AR_BASE+8, "ar8" },
+ { REG_AR_BASE+9, "ar9" },
+ { REG_AR_BASE+10, "ar10" },
+ { REG_AR_BASE+11, "ar11" },
+ { REG_AR_BASE+12, "ar12" },
+ { REG_AR_BASE+13, "ar13" },
+ { REG_AR_BASE+14, "ar14" },
+ { REG_AR_BASE+15, "ar15" },
+ { REG_AR_BASE+16, "ar16" },
+ { REG_AR_BASE+17, "ar17" },
+ { REG_AR_BASE+18, "ar18" },
+ { REG_AR_BASE+19, "ar19" },
+ { REG_AR_BASE+20, "ar20" },
+ { REG_AR_BASE+21, "ar21" },
+ { REG_AR_BASE+22, "ar22" },
+ { REG_AR_BASE+23, "ar23" },
+ { REG_AR_BASE+24, "ar24" },
+ { REG_AR_BASE+25, "ar25" },
+ { REG_AR_BASE+26, "ar26" },
+ { REG_AR_BASE+27, "ar27" },
+ { REG_AR_BASE+28, "ar28" },
+ { REG_AR_BASE+29, "ar29" },
+ { REG_AR_BASE+30, "ar30" },
+ { REG_AR_BASE+31, "ar31" },
+ { REG_AR_BASE+32, "ar32" },
+ { REG_AR_BASE+33, "ar33" },
+ { REG_AR_BASE+34, "ar34" },
+ { REG_AR_BASE+35, "ar35" },
+ { REG_AR_BASE+36, "ar36" },
+ { REG_AR_BASE+37, "ar37" },
+ { REG_AR_BASE+38, "ar38" },
+ { REG_AR_BASE+39, "ar39" },
+ { REG_AR_BASE+40, "ar40" },
+ { REG_AR_BASE+41, "ar41" },
+ { REG_AR_BASE+42, "ar42" },
+ { REG_AR_BASE+43, "ar43" },
+ { REG_AR_BASE+44, "ar44" },
+ { REG_AR_BASE+45, "ar45" },
+ { REG_AR_BASE+46, "ar46" },
+ { REG_AR_BASE+47, "ar47" },
+ { REG_AR_BASE+48, "ar48" },
+ { REG_AR_BASE+49, "ar49" },
+ { REG_AR_BASE+50, "ar50" },
+ { REG_AR_BASE+51, "ar51" },
+ { REG_AR_BASE+52, "ar52" },
+ { REG_AR_BASE+53, "ar53" },
+ { REG_AR_BASE+54, "ar54" },
+ { REG_AR_BASE+55, "ar55" },
+ { REG_AR_BASE+56, "ar56" },
+ { REG_AR_BASE+57, "ar57" },
+ { REG_AR_BASE+58, "ar58" },
+ { REG_AR_BASE+59, "ar59" },
+ { REG_AR_BASE+60, "ar60" },
+ { REG_AR_BASE+61, "ar61" },
+ { REG_AR_BASE+62, "ar62" },
+ { REG_AR_BASE+63, "ar63" },
+ { REG_LBEG, "lbeg" },
+ { REG_LEND, "lend" },
+ { REG_LCOUNT, "lcount" },
+ { REG_SAR, "sar" },
+ { REG_WB, "wb" },
+ { REG_WS, "ws" },
+ { REG_PS, "ps" },
+ { REG_PC, "pc" },
+ { REG_A_BASE, "a0" },
+ { REG_A_BASE+1, "a1" },
+ { REG_A_BASE+2, "a2" },
+ { REG_A_BASE+3, "a3" },
+ { REG_A_BASE+4, "a4" },
+ { REG_A_BASE+5, "a5" },
+ { REG_A_BASE+6, "a6" },
+ { REG_A_BASE+7, "a7" },
+ { REG_A_BASE+8, "a8" },
+ { REG_A_BASE+9, "a9" },
+ { REG_A_BASE+10, "a10" },
+ { REG_A_BASE+11, "a11" },
+ { REG_A_BASE+12, "a12" },
+ { REG_A_BASE+13, "a13" },
+ { REG_A_BASE+14, "a14" },
+ { REG_A_BASE+15, "a15" },
+#endif
+
+ /* Other fields in "struct user" */
+#if defined(S390) || defined(S390X)
+ { uoff(u_tsize), "offsetof(struct user, u_tsize)" },
+ { uoff(u_dsize), "offsetof(struct user, u_dsize)" },
+ { uoff(u_ssize), "offsetof(struct user, u_ssize)" },
+ { uoff(start_code), "offsetof(struct user, start_code)" },
+ /* S390[X] has no start_data */
+ { uoff(start_stack), "offsetof(struct user, start_stack)" },
+ { uoff(signal), "offsetof(struct user, signal)" },
+ { uoff(u_ar0), "offsetof(struct user, u_ar0)" },
+ { uoff(magic), "offsetof(struct user, magic)" },
+ { uoff(u_comm), "offsetof(struct user, u_comm)" },
+ { sizeof(struct user), "sizeof(struct user)" },
+#elif defined(POWERPC)
+ { sizeof(struct user), "sizeof(struct user)" },
+#elif defined(I386) || defined(X86_64) || defined(X32)